This invention relates to computer systems and their operation and particularly to data persistence within a multi-node system.
Historically, data persistence within a multi-node computer system has been a focus of computer system architecture inasmuch as it avoids stalling of processor requests and the negative impact such stalling may have on overall system performance. As here used, reference to a node means an organization of one or more processors and a memory array operatively associated with the processor(s) which has main memory and one or more levels of cache interposed between the processor(s) and the main memory. Reference to a multi-node system, then means an organization of a plurality of nodes.
Algorithms and design methods intended to minimize and avoid stalling typically have taken only a few forms. The most straight forward of these is an increase in the number and size of cache(s) within a system. In this approach, data persistence is addressed through an overall increase in cache space and improves through the simple increase in the number of lines which can be stored in cache and the length of their tenure in a given cache.
Another approach has been through improved cache line replacement algorithms, which work under the premise that a more intelligent selection of cache lines for eviction, when a new line install is required, will result in the persistence of the most relevant data. The assumption is that a subsequent fetch is more likely to encounter a hit in the remaining lines of code instead of the evicted lines.
Yet another approach is by way of pre-fetch algorithms, which do not directly address data persistence by definition, but instead seek to predict lines of future importance and bring them toward the processor(s) in a timely manner.
With all of these approaches, the technologies generally do well in address the issue of data persistence in various forms. However, they have consistently been focused on what is here described as the vertical aspect of a cache structure. While this characterization will be expanded on in the discussion which follows, it can here be noted that the vertical aspect describes the data path to or from a processor or processor complex through associated levels of cache directly associated with that processor or processor complex and from or to a main memory element directly associated with that processor or processor complex.
What is described here as the present invention focuses more on horizontal aspects of cache design, particularly in a multi-node system.